技术可行的直流性能元件为Si/SiGe通道CMOS FinFTT

2016 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2016-12-01 DOI:10.1109/IEDM.2016.7838439

G. Tsutsui, R. Bao, K. Lim, R. Robison, R. Vega, Jie Yang, Zuoguang Liu, Miaomiao Wang, O. Gluschenkov, C. Yeung, Koji Watanabe, S. Bentley, H. Niimi, Derrick Liu, Huimei Zhou, S. Siddiqui, Hoon Kim, R. Galatage, R. Venigalla, M. Raymond, P. Adusumilli, S. Mochizuki, T. Devarajan, Bruce Miao, Bei Liu, A. Greene, J. Shearer, P. Montanini, J. Strane, C. Prindle, E. Miller, J. Fronheiser, C. Niu, K. Chung, J. Kelly, H. Jagannathan, S. Kanakasabapathy, G. Karve, F. Lie, P. Oldiges, V. Narayanan, T. Hook, A. Knorr, D. Gupta, D. Guo, R. Divakaruni, H. Bu, M. Khare

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引用次数: 8

摘要

低锗含量基于硅基CMOS FinFET是一种有前途的技术[1-2]，为高性能和低功耗应用提供解决方案。在本文中，我们建立了一个具有竞争力的基于sigs的CMOS FinFET基线，并检查了高性能产品的各种元素。对栅极堆叠、沟道掺杂、接触电阻和结中的性能要素进行了探索，以提供累积20% / 25% (n/ fet)的性能增强。这些元素为未来技术节点的性能增强提供了可行的途径。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

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来源期刊

2016 IEEE International Electron Devices Meeting (IEDM)

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