{"title":"基于recc的片上系统拓扑结构的综合和无死锁路由算法","authors":"M.B. Stuart, M. B. Stensgaard, J. Sparsø","doi":"10.1145/1629435.1629500","DOIUrl":null,"url":null,"abstract":"In the near future, generic System-on-Chip (SoC) platforms will be replacing custom designed SoCs. Such generic platforms require a highly flexible interconnect in order to support a wide variety of applications. The ReNoC architecture provides this by allowing power efficient, application specific topologies to be configured on top of a fixed but reconfigurable physical architecture through a mixture of packet switching and physical circuit switching.\n The first contribution of this paper is three novel algorithms that, given an abstract description of the application and the physical architecture, 1) synthesize the application specific topologies, 2) map them onto the physical architecture, and 3) create deadlock free, application specific routing algorithms.\n The second contribution is a novel physical architecture based on an extended mesh of ReNoC nodes. We apply our algorithms to a mixture of real and synthetic applications and three different physical architectures. Our results show that the different algorithms' performance are highly dependent on the physical architecture. On average, our novel physical architecture reduces power consumption by 58% compared to a conventional Network-on-Chip.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip\",\"authors\":\"M.B. Stuart, M. B. Stensgaard, J. Sparsø\",\"doi\":\"10.1145/1629435.1629500\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the near future, generic System-on-Chip (SoC) platforms will be replacing custom designed SoCs. Such generic platforms require a highly flexible interconnect in order to support a wide variety of applications. The ReNoC architecture provides this by allowing power efficient, application specific topologies to be configured on top of a fixed but reconfigurable physical architecture through a mixture of packet switching and physical circuit switching.\\n The first contribution of this paper is three novel algorithms that, given an abstract description of the application and the physical architecture, 1) synthesize the application specific topologies, 2) map them onto the physical architecture, and 3) create deadlock free, application specific routing algorithms.\\n The second contribution is a novel physical architecture based on an extended mesh of ReNoC nodes. We apply our algorithms to a mixture of real and synthetic applications and three different physical architectures. Our results show that the different algorithms' performance are highly dependent on the physical architecture. On average, our novel physical architecture reduces power consumption by 58% compared to a conventional Network-on-Chip.\",\"PeriodicalId\":300268,\"journal\":{\"name\":\"International Conference on Hardware/Software Codesign and System Synthesis\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-10-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Hardware/Software Codesign and System Synthesis\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1629435.1629500\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Hardware/Software Codesign and System Synthesis","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1629435.1629500","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip
In the near future, generic System-on-Chip (SoC) platforms will be replacing custom designed SoCs. Such generic platforms require a highly flexible interconnect in order to support a wide variety of applications. The ReNoC architecture provides this by allowing power efficient, application specific topologies to be configured on top of a fixed but reconfigurable physical architecture through a mixture of packet switching and physical circuit switching.
The first contribution of this paper is three novel algorithms that, given an abstract description of the application and the physical architecture, 1) synthesize the application specific topologies, 2) map them onto the physical architecture, and 3) create deadlock free, application specific routing algorithms.
The second contribution is a novel physical architecture based on an extended mesh of ReNoC nodes. We apply our algorithms to a mixture of real and synthetic applications and three different physical architectures. Our results show that the different algorithms' performance are highly dependent on the physical architecture. On average, our novel physical architecture reduces power consumption by 58% compared to a conventional Network-on-Chip.