一种10位50MS/s低压低功率流水线ADC的研究

2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI:10.1109/ICSICT.2008.4734951

Cuncai Zhang, Hui Wang, Yuhua Cheng

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引用次数: 2

摘要

本文介绍了一种10位50毫秒/秒的模数转换器(ADC)。采用低功率增益增强运算放大器和动态比较器，设计功耗为10.6 mW。自举开关实现低压电源的轨间信号摆动。该电路采用中芯国际1.2 v 0.13 um CMOS技术设计。结果表明，所提出的奈奎斯特速率ADC为DVB-H、DVB-T和wlan等低功耗高速应用提供了一种潜在的解决方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A study of a10-bit 50MS/s low voltage low power pipelined ADC

In this paper, a 10-bit 50-MS/s analog-to-digital converter (ADC) is presented. A power consumption of 10.6 mW is designed by using low power gain-boosted OP-Amp and dynamic comparator. Bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. This circuit is designed in a SMIC 1.2-V 0.13-um CMOS technology. The results show that the proposed Nyquist rate ADC provides a potential solution for low-power high-speed applications, e.g., DVB-H, DVB-T and WLANs.

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

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