J. Lindeberg, Olli Väänänen, J. Pirkkalaniemi, M. Kosunen, K. Halonen
{"title":"带有数字中频和片上D/ a转换器的OFDM调制器","authors":"J. Lindeberg, Olli Väänänen, J. Pirkkalaniemi, M. Kosunen, K. Halonen","doi":"10.1109/CICC.2006.320907","DOIUrl":null,"url":null,"abstract":"A digital OFDM modulator with 2048-point IFFT and 83.2 MHz bandwidth is implemented. The modulator consists of IFFT block, upsampling filters and upconversion included in the upsampling operation. Also a clipping unit is implemented before the on-chip D/A-converter in order to efficiently utilise the whole dynamic range of the converter and to maximise the power efficiency of the power amplifier. An inverse sine block is added to compensate the D/A-converter's sine response. The digital IF signal is converted to analog signal by using a 10-bit on-chip D/A-converter with sampling frequency of 819.2 MHz and center frequency of 204.8 MHz. The IFFT block is implemented with FPGA device and the rest of the system is fabricated in a 90 nm CMOS process","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"201 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"OFDM modulator with digital IF and on-chip D/A-converter\",\"authors\":\"J. Lindeberg, Olli Väänänen, J. Pirkkalaniemi, M. Kosunen, K. Halonen\",\"doi\":\"10.1109/CICC.2006.320907\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A digital OFDM modulator with 2048-point IFFT and 83.2 MHz bandwidth is implemented. The modulator consists of IFFT block, upsampling filters and upconversion included in the upsampling operation. Also a clipping unit is implemented before the on-chip D/A-converter in order to efficiently utilise the whole dynamic range of the converter and to maximise the power efficiency of the power amplifier. An inverse sine block is added to compensate the D/A-converter's sine response. The digital IF signal is converted to analog signal by using a 10-bit on-chip D/A-converter with sampling frequency of 819.2 MHz and center frequency of 204.8 MHz. The IFFT block is implemented with FPGA device and the rest of the system is fabricated in a 90 nm CMOS process\",\"PeriodicalId\":269854,\"journal\":{\"name\":\"IEEE Custom Integrated Circuits Conference 2006\",\"volume\":\"201 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Custom Integrated Circuits Conference 2006\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2006.320907\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Custom Integrated Circuits Conference 2006","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2006.320907","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
OFDM modulator with digital IF and on-chip D/A-converter
A digital OFDM modulator with 2048-point IFFT and 83.2 MHz bandwidth is implemented. The modulator consists of IFFT block, upsampling filters and upconversion included in the upsampling operation. Also a clipping unit is implemented before the on-chip D/A-converter in order to efficiently utilise the whole dynamic range of the converter and to maximise the power efficiency of the power amplifier. An inverse sine block is added to compensate the D/A-converter's sine response. The digital IF signal is converted to analog signal by using a 10-bit on-chip D/A-converter with sampling frequency of 819.2 MHz and center frequency of 204.8 MHz. The IFFT block is implemented with FPGA device and the rest of the system is fabricated in a 90 nm CMOS process