{"title":"一种高效全数字锁相环的实现","authors":"Haritha G. Krishnan, R. P.","doi":"10.1109/ASIANCON55314.2022.9909292","DOIUrl":null,"url":null,"abstract":"The creation of an efficient All Digital Phase Locked Loop is demonstrated in this study (ADPLL).The work is initiated to analyze the ways in which the components of an ADPLL network could be designed from the pool. The proposed ADPLL network is chosen in such a way to improve its efficiency from that of previous studies. The Design is modeled using VERILOG Hardware Description language (HDL) and analyzed using Xilinx ISE 9.1,spartan3 family,XC3S4000L.At last the efficiency of the design is analyzed from the previous works by considering various parameters","PeriodicalId":429704,"journal":{"name":"2022 2nd Asian Conference on Innovation in Technology (ASIANCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Implementation Of An Efficient All Digital Phase Locked Loop\",\"authors\":\"Haritha G. Krishnan, R. P.\",\"doi\":\"10.1109/ASIANCON55314.2022.9909292\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The creation of an efficient All Digital Phase Locked Loop is demonstrated in this study (ADPLL).The work is initiated to analyze the ways in which the components of an ADPLL network could be designed from the pool. The proposed ADPLL network is chosen in such a way to improve its efficiency from that of previous studies. The Design is modeled using VERILOG Hardware Description language (HDL) and analyzed using Xilinx ISE 9.1,spartan3 family,XC3S4000L.At last the efficiency of the design is analyzed from the previous works by considering various parameters\",\"PeriodicalId\":429704,\"journal\":{\"name\":\"2022 2nd Asian Conference on Innovation in Technology (ASIANCON)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-08-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 2nd Asian Conference on Innovation in Technology (ASIANCON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIANCON55314.2022.9909292\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 2nd Asian Conference on Innovation in Technology (ASIANCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIANCON55314.2022.9909292","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
本研究演示了一个高效的全数字锁相环(ADPLL)的创建。这项工作的开始是分析ADPLL网络的组件可以从池中设计的方法。本文选择的ADPLL网络是为了在前人研究的基础上提高其效率。本设计采用VERILOG硬件描述语言(HDL)进行建模，并使用Xilinx ISE 9.1,spartan3系列，XC3S4000L进行分析。最后，综合考虑各参数对设计的效率进行了分析
Implementation Of An Efficient All Digital Phase Locked Loop
The creation of an efficient All Digital Phase Locked Loop is demonstrated in this study (ADPLL).The work is initiated to analyze the ways in which the components of an ADPLL network could be designed from the pool. The proposed ADPLL network is chosen in such a way to improve its efficiency from that of previous studies. The Design is modeled using VERILOG Hardware Description language (HDL) and analyzed using Xilinx ISE 9.1,spartan3 family,XC3S4000L.At last the efficiency of the design is analyzed from the previous works by considering various parameters
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