{"title":"具有增强抗噪能力的双输入8晶体管SRAM单元","authors":"A. Korotkov, D. Morozov, J. Hauer","doi":"10.1109/ISFEE.2016.7803191","DOIUrl":null,"url":null,"abstract":"The paper presents eight transistors SRAM cell with improved noise (interferences) immunity. The effect is reached by use an additional bus to control the state of the cell trigger. The results of the simulations as well as experiments have been demonstrated. The following SRAM characteristics have been obtained SNM = 222 mV, WRM = 1017 mV, the cell discharge current is 114 uA. The test chip has been fabricated with parameters of 180 nm CMOS process of UMC.","PeriodicalId":240170,"journal":{"name":"2016 International Symposium on Fundamentals of Electrical Engineering (ISFEE)","volume":"442 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A two-input 8-transistor SRAM cell with enhanced noise immunity\",\"authors\":\"A. Korotkov, D. Morozov, J. Hauer\",\"doi\":\"10.1109/ISFEE.2016.7803191\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents eight transistors SRAM cell with improved noise (interferences) immunity. The effect is reached by use an additional bus to control the state of the cell trigger. The results of the simulations as well as experiments have been demonstrated. The following SRAM characteristics have been obtained SNM = 222 mV, WRM = 1017 mV, the cell discharge current is 114 uA. The test chip has been fabricated with parameters of 180 nm CMOS process of UMC.\",\"PeriodicalId\":240170,\"journal\":{\"name\":\"2016 International Symposium on Fundamentals of Electrical Engineering (ISFEE)\",\"volume\":\"442 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Symposium on Fundamentals of Electrical Engineering (ISFEE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISFEE.2016.7803191\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Symposium on Fundamentals of Electrical Engineering (ISFEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISFEE.2016.7803191","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A two-input 8-transistor SRAM cell with enhanced noise immunity
The paper presents eight transistors SRAM cell with improved noise (interferences) immunity. The effect is reached by use an additional bus to control the state of the cell trigger. The results of the simulations as well as experiments have been demonstrated. The following SRAM characteristics have been obtained SNM = 222 mV, WRM = 1017 mV, the cell discharge current is 114 uA. The test chip has been fabricated with parameters of 180 nm CMOS process of UMC.
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