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引用次数: 4
摘要
由于电路中涉及的各种因素,大多数电子电路元件不能同时接收时钟。锁相环是一种高频、高精度、联锁时间极短的精密电路。本文介绍了全数字锁相环(ADPLL),并在其成本、功耗和锁相环运行速度的基础上,对其应用进行了分析。在给定的ADPLL系统中,相位检测系统是通过希尔伯特变换产生解析信号,然后用CORDIC算法计算瞬时相位来实现的。ADPLL的环路滤波器采用低通滤波器设计,用于去除高次谐波。所提出的架构使用VHDL代码实现,并使用Xilinx ISE 9.2软件进行综合。为了验证其功能,可以使用Modelsim SE 6.2C进行验证和仿真。ADPLL的中心频率为100mhz。本文主要研究了ADPLL的功率效率问题。
FPGA implementation and power efficient CORDIC based ADPLL for signal processing and application
Most of the electronic circuit components do not receive the clock at same time due to various factors involved in circuitry. Phase locked loop is a precision and familiar circuit for high frequency and high accuracy application with very short interlocking time. This paper presents All Digital Phase Locked Loop (ADPLL) and has been analysed for the required applications on the basis of its cost, power consumption and speed of operation for phase locked loop. In the given ADPLL system phase detection system has been realized by generating analytic signal using Hilbert transform and then computing the instantaneous phase using CORDIC algorithm. The loop filter of the ADPLL has been designed using a low pass filter and is used to discard the higher order harmonics. The proposed architecture is implemented using VHDL code and is synthesized using Xilinx ISE 9.2 software. To validate its functionality, verification and simulation is done by using the Modelsim SE 6.2C. The ADPLL is planned for 100 MHz central frequency. The work in this paper mainly deals with the power efficiency of ADPLL.