Two VLSI structures for implementing the gray level co-occurrence method

The gray-level co-occurrence (GLC) method is a powerful technique that computes several GLC matrices on subregions of an image to measure its textural qualities. The method is not suitable for real-time image analysis and pattern recognition because of its high compute time. The authors propose a systolic array and a parallel architecture for evaluating the algorithm in an optimum time. Novel features of the structures include the minimization of intermediate I/O operations and the use of current existing hardware devices. The architectures are time optimal and are suitable for algorithm partitioning.<>