带分流阵列的数字校准电流转向DAC

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI:10.1109/MWSCAS.2012.6292011

Long Cheng, Chixiao Chen, Fan Ye, Ning Li, Junyan Ren

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引用次数: 4

摘要

电流导向DAC的分流结构可以大大减小电流源阵列的面积。提出了一种基于分流阵列的电流转向数模(DAC)背景标定技术。所提出的校正技术可以消除背景中上位阵列和下位阵列的不匹配误差。采用0.18μm CMOS工艺制备了14位电流转向DAC。SFDR可提高20dB以上。该DAC在2MHz下可实现超过80dB的SFDR，采样率为200MS/s。有效面积为1.26mm2，功耗为125mW。

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A digitally calibrated current-steering DAC with current-splitting array

The current-splitting architecture for the current-steering DAC can reduce the area of the current source array greatly. A background calibration technique for current-steering digital-to-analog (DAC) with the current-splitting array is presented. The proposed calibration technique can eliminate mismatch errors for both the upper bits array and the lower bits array in the background. A 14-bit current-steering DAC is fabricated in a 0.18μm CMOS process. The SFDR can be improved more than 20dB. The DAC achieves more than 80dB SFDR at 2MHz for a 200MS/s sampling rate. The active area is 1.26mm2 and power consumption is 125mW.

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2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)

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