{"title":"Scratchpad内存-全局功率优化","authors":"M. Karthika, C. Rajasekaran","doi":"10.1109/ICPRIME.2012.6208343","DOIUrl":null,"url":null,"abstract":"Scratchpad Memories are widely employed in embedded systems as an alternative to caches because they achieve comparable performance with higher power efficiency. Here, Optimal SPM Mapping and Memory Power-Down techniques are used for minimize the total energy of the SPM. SPM mapping simply targets the minimum number of accesses to the main memory, i.e., active power. A global optimization should explicitly take into account memory access energy, leakage energy, and power-down/up energy penalty, to define the Optimal SPM mapping and Optimal memory power-down scheduling for minimizing the total energy in the memory sub-system. Synthesis results based on 1.32V CMOS standard-cell library shows that the proposed SPM reduces the power consumption by 25-30%.","PeriodicalId":148511,"journal":{"name":"International Conference on Pattern Recognition, Informatics and Medical Engineering (PRIME-2012)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Scratchpad memory-global power optimization\",\"authors\":\"M. Karthika, C. Rajasekaran\",\"doi\":\"10.1109/ICPRIME.2012.6208343\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Scratchpad Memories are widely employed in embedded systems as an alternative to caches because they achieve comparable performance with higher power efficiency. Here, Optimal SPM Mapping and Memory Power-Down techniques are used for minimize the total energy of the SPM. SPM mapping simply targets the minimum number of accesses to the main memory, i.e., active power. A global optimization should explicitly take into account memory access energy, leakage energy, and power-down/up energy penalty, to define the Optimal SPM mapping and Optimal memory power-down scheduling for minimizing the total energy in the memory sub-system. Synthesis results based on 1.32V CMOS standard-cell library shows that the proposed SPM reduces the power consumption by 25-30%.\",\"PeriodicalId\":148511,\"journal\":{\"name\":\"International Conference on Pattern Recognition, Informatics and Medical Engineering (PRIME-2012)\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-03-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Pattern Recognition, Informatics and Medical Engineering (PRIME-2012)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICPRIME.2012.6208343\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Pattern Recognition, Informatics and Medical Engineering (PRIME-2012)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICPRIME.2012.6208343","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Scratchpad Memories are widely employed in embedded systems as an alternative to caches because they achieve comparable performance with higher power efficiency. Here, Optimal SPM Mapping and Memory Power-Down techniques are used for minimize the total energy of the SPM. SPM mapping simply targets the minimum number of accesses to the main memory, i.e., active power. A global optimization should explicitly take into account memory access energy, leakage energy, and power-down/up energy penalty, to define the Optimal SPM mapping and Optimal memory power-down scheduling for minimizing the total energy in the memory sub-system. Synthesis results based on 1.32V CMOS standard-cell library shows that the proposed SPM reduces the power consumption by 25-30%.