{"title":"一个1.3 μ m的BiCMOS门阵列，具有可配置的片上3端口RAM","authors":"T. Wong, M. El-Khatib","doi":"10.1109/ASIC.1989.123187","DOIUrl":null,"url":null,"abstract":"A 10 K-gate BiCMOS gate array with a configurable 4.6-kb SRAM (static RAM) has been developed using a 1.3- mu m technology. The propagation delay time of a two-input NAND is 0.45 ns at 0.6-pF load. The on-chip memory can be configured as *9, *18, *36 b. A description is given of the device structure, the basic cell design, the memory configuration, and the performance of this memory-plus-logic combination.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 1.3 mu m BiCMOS gate array with configurable on-chip 3-port RAM\",\"authors\":\"T. Wong, M. El-Khatib\",\"doi\":\"10.1109/ASIC.1989.123187\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 10 K-gate BiCMOS gate array with a configurable 4.6-kb SRAM (static RAM) has been developed using a 1.3- mu m technology. The propagation delay time of a two-input NAND is 0.45 ns at 0.6-pF load. The on-chip memory can be configured as *9, *18, *36 b. A description is given of the device structure, the basic cell design, the memory configuration, and the performance of this memory-plus-logic combination.<<ETX>>\",\"PeriodicalId\":245997,\"journal\":{\"name\":\"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-09-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1989.123187\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1989.123187","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.3 mu m BiCMOS gate array with configurable on-chip 3-port RAM
A 10 K-gate BiCMOS gate array with a configurable 4.6-kb SRAM (static RAM) has been developed using a 1.3- mu m technology. The propagation delay time of a two-input NAND is 0.45 ns at 0.6-pF load. The on-chip memory can be configured as *9, *18, *36 b. A description is given of the device structure, the basic cell design, the memory configuration, and the performance of this memory-plus-logic combination.<>
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
