{"title":"使用传统和分层结构风格的64位进位前瞻加法器的性能分析","authors":"Abdulmajeed Alghamdi, F. Gebali","doi":"10.1109/PACRIM.2015.7334813","DOIUrl":null,"url":null,"abstract":"This paper introduces performance analysis of 64-bit Carry Lookahead Adders using conventional and hierarchical structure styles. We evaluate conventional carry lookahead adder (CLA) and hierarchical carry lookahead adder (HCLA) using different parameters. Our design is targeted into FPGA Virtex 7 family. Area, delay, and area-delay product of all design choices are reported. In the experimental results, we reduced CLA delay and area using radix-2 which performed better than traditionally used radix-4 CLA. In addition, we showed that CLA using conventional structure has better performance than the hierarchical structure.","PeriodicalId":350052,"journal":{"name":"2015 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Performance analysis of 64-bit Carry Lookahead Adders using conventional and hierarchical structure styles\",\"authors\":\"Abdulmajeed Alghamdi, F. Gebali\",\"doi\":\"10.1109/PACRIM.2015.7334813\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces performance analysis of 64-bit Carry Lookahead Adders using conventional and hierarchical structure styles. We evaluate conventional carry lookahead adder (CLA) and hierarchical carry lookahead adder (HCLA) using different parameters. Our design is targeted into FPGA Virtex 7 family. Area, delay, and area-delay product of all design choices are reported. In the experimental results, we reduced CLA delay and area using radix-2 which performed better than traditionally used radix-4 CLA. In addition, we showed that CLA using conventional structure has better performance than the hierarchical structure.\",\"PeriodicalId\":350052,\"journal\":{\"name\":\"2015 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PACRIM.2015.7334813\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PACRIM.2015.7334813","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Performance analysis of 64-bit Carry Lookahead Adders using conventional and hierarchical structure styles
This paper introduces performance analysis of 64-bit Carry Lookahead Adders using conventional and hierarchical structure styles. We evaluate conventional carry lookahead adder (CLA) and hierarchical carry lookahead adder (HCLA) using different parameters. Our design is targeted into FPGA Virtex 7 family. Area, delay, and area-delay product of all design choices are reported. In the experimental results, we reduced CLA delay and area using radix-2 which performed better than traditionally used radix-4 CLA. In addition, we showed that CLA using conventional structure has better performance than the hierarchical structure.