使用传统和分层结构风格的64位进位前瞻加法器的性能分析

Abdulmajeed Alghamdi, F. Gebali
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引用次数: 5

摘要

本文介绍了64位进位前瞻加法器的性能分析,包括传统结构和分层结构。我们用不同的参数对传统进位前瞻加法器(CLA)和分层进位前瞻加法器(HCLA)进行了评价。本设计针对的是Virtex 7系列FPGA。报告了所有设计选择的面积、延迟和面积延迟产品。在实验结果中,我们使用基数2降低了CLA延迟和面积,比传统的基数4 CLA性能更好。此外,我们还发现使用常规结构的CLA比使用分层结构的CLA具有更好的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Performance analysis of 64-bit Carry Lookahead Adders using conventional and hierarchical structure styles
This paper introduces performance analysis of 64-bit Carry Lookahead Adders using conventional and hierarchical structure styles. We evaluate conventional carry lookahead adder (CLA) and hierarchical carry lookahead adder (HCLA) using different parameters. Our design is targeted into FPGA Virtex 7 family. Area, delay, and area-delay product of all design choices are reported. In the experimental results, we reduced CLA delay and area using radix-2 which performed better than traditionally used radix-4 CLA. In addition, we showed that CLA using conventional structure has better performance than the hierarchical structure.
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