Chang-Su Kim, Hong-bae Park, Bung-Gwan Kim, D. Kang, Myoung-Goo Lee, Siwon Lee, Chan-Hee Jeon, Wan-Gu Kim, Young-Jae Yoo, H. Yoon
{"title":"一种新型的NMOS晶体管,用于高性能ESD保护器件,采用0.18 /spl mu/m CMOS技术,采用盐化工艺","authors":"Chang-Su Kim, Hong-bae Park, Bung-Gwan Kim, D. Kang, Myoung-Goo Lee, Siwon Lee, Chan-Hee Jeon, Wan-Gu Kim, Young-Jae Yoo, H. Yoon","doi":"10.1109/EOSESD.2000.890109","DOIUrl":null,"url":null,"abstract":"The electrostatic discharge (ESD) threshold of fully salicided grounded-gate NMOS transistors (ggNMOSTs) and partially salicided ggNMOSTs consisting of dummy-gate and N-well resistor was studied by transmission line pulse (TLP) I-V curves, and HBM and machine model (MM) robustness. The state-of-the-art 0.18 /spl mu/m cobalt salicide CMOS process is used, and the thickness of the gate dielectric material is 35 /spl Aring/. Fully salicided ggNMOSTs have much lower values of second breakdown current (It2) than partially salicided ggNMOSTs, and with multi-finger structures, only partially salicided ggNMOSTs turn on uniformly. Using these partially salicided NMOSTs as protection devices, we acquired ESD immunity of >2 kV (HBM) and >200 V (MM).","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"A novel NMOS transistor for high performance ESD protection devices in 0.18 /spl mu/m CMOS technology utilizing salicide process\",\"authors\":\"Chang-Su Kim, Hong-bae Park, Bung-Gwan Kim, D. Kang, Myoung-Goo Lee, Siwon Lee, Chan-Hee Jeon, Wan-Gu Kim, Young-Jae Yoo, H. Yoon\",\"doi\":\"10.1109/EOSESD.2000.890109\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The electrostatic discharge (ESD) threshold of fully salicided grounded-gate NMOS transistors (ggNMOSTs) and partially salicided ggNMOSTs consisting of dummy-gate and N-well resistor was studied by transmission line pulse (TLP) I-V curves, and HBM and machine model (MM) robustness. The state-of-the-art 0.18 /spl mu/m cobalt salicide CMOS process is used, and the thickness of the gate dielectric material is 35 /spl Aring/. Fully salicided ggNMOSTs have much lower values of second breakdown current (It2) than partially salicided ggNMOSTs, and with multi-finger structures, only partially salicided ggNMOSTs turn on uniformly. Using these partially salicided NMOSTs as protection devices, we acquired ESD immunity of >2 kV (HBM) and >200 V (MM).\",\"PeriodicalId\":332394,\"journal\":{\"name\":\"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-09-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EOSESD.2000.890109\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EOSESD.2000.890109","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel NMOS transistor for high performance ESD protection devices in 0.18 /spl mu/m CMOS technology utilizing salicide process
The electrostatic discharge (ESD) threshold of fully salicided grounded-gate NMOS transistors (ggNMOSTs) and partially salicided ggNMOSTs consisting of dummy-gate and N-well resistor was studied by transmission line pulse (TLP) I-V curves, and HBM and machine model (MM) robustness. The state-of-the-art 0.18 /spl mu/m cobalt salicide CMOS process is used, and the thickness of the gate dielectric material is 35 /spl Aring/. Fully salicided ggNMOSTs have much lower values of second breakdown current (It2) than partially salicided ggNMOSTs, and with multi-finger structures, only partially salicided ggNMOSTs turn on uniformly. Using these partially salicided NMOSTs as protection devices, we acquired ESD immunity of >2 kV (HBM) and >200 V (MM).