Enhanced prediction of energy losses during adiabatic charging [CMOS circuit]

Since its more general introduction, adiabatic charging has been considered to have a more or less unlimited potential to reduce the power consumption of a CMOS circuit. The prediction was that when reducing operation speed the power consumption could be decreased unlimited, in extreme down to zero. However, if static losses are considered, too, a limit for the achievable minimum power consumption occurs, stating an optimum charging time with minimal power consumption, that is different from infinity, in opposition to the well known considerations used up to now. A linear network model giving the reason for such losses is introduced in this paper, together with a closed formula for the prediction of the power consumption of such a circuit. From this formula the optimum charging time and minimal power consumption can be derived, in closed form, too. Further it is shown, that for such circuits with static losses the well-known linear charging ramps do no longer form the optimal waveform for charging with low losses. These waveforms can be derived by variational calculus. By comparing the predicted energy losses to simulation results gained by using the models of a standard CMOS process, it is shown that the linear model holds in the interesting range of charging times, giving a rather precise description.