An FPGA-Based Identifier Mapping Module Design for Space-Air-Ground Integrated Network

In the space-air-ground integrated network (SAGIN) based on identifier mapping protocol (IDP), IDP separates user space and network space apart, which is difficult for traditional networks to accomplish. The communication quality and topology between satellites change rapidly in the actual environment, so high-quality satellite communication requires satellite nodes to process data packets with a lower delay. However, the previous software-based implementation scheme is limited by Von Neumann Architecture, which is hard to greatly reduce the processing delay. Not all the content in the IDP stack needs to be processed flexibly, so that FPGA can be used for accelerating the parts with high locality and repetitiveness. To provide lower latency for identifier mapping in future deployment, this paper proposes an FPGA-based identifier mapping module design, which hardwareizes the mapping process and demapping process between IP address and the routing identifier (RID) in the identifier switch router (IDSR) deployed on the satellite. Meanwhile, to further shorten the average processing delay, this design adopts Least-Recently-Used (LRU) algorithm for optimization. This paper describes the framework of the design in detail, and the experiment results in the emulation environment prove that the mapping processing delay of the FPGA-based identifier mapping module design is able to provide a lower delay for IDSR in SAGIN.