通过算法增强和连接感知并行化加速FPGA路由

Yun Zhou, Dries Vercruyce, D. Stroobandt
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引用次数: 11

摘要

路由是现场可编程门阵列(FPGA)物理设计中的关键步骤,它决定了电路中信号的路由,对设计的实现质量有重要影响。成功地路由利用许多FPGA资源的大型电路的所有信号可能非常耗时。在期望高质量实现的同时,已经尝试缩短路由运行时以进行有效的设计探索。在这项工作中,我们详细阐述了基于连接的路由策略和算法改进,以改进串行FPGA路由。我们还探索了一种基于递归分区的并行化技术,以进一步加速路由过程。为了在空间划分和路由中通过更细的粒度实现更多的并行性,提出了一种基于连接感知的网络源-汇连接路由边界盒模型。它是建立在每个连接的源、接收器和连接所属网络的几何中心的位置信息之上的,不同于现有的基于网络的路由包围盒,它覆盖了整个网络的所有引脚。我们提出的连接感知路由边界盒比现有的基于网络的路由边界盒更有利于并行路由。将串行和多线程路由器的质量和运行时间与VPR 7.0.7中的路由器进行了比较。针对Stratix IV FPGA的详细表示的大型异构Titan23设计用于基准测试。在VPR 7.0.7版本下,采用连接感知路由边界盒模型的并行路由器在8个线程下的速度比串行路由器提高了6.1倍,比现有基于网络的路由边界盒模型提高了1.24倍,同时总线长减少了10%,关键路径延迟减少了7%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Accelerating FPGA Routing Through Algorithmic Enhancements and Connection-aware Parallelization
Routing is a crucial step in Field Programmable Gate Array (FPGA) physical design, as it determines the routes of signals in the circuit, which impacts the design implementation quality significantly. It can be very time-consuming to successfully route all the signals of large circuits that utilize many FPGA resources. Attempts have been made to shorten the routing runtime for efficient design exploration while expecting high-quality implementations. In this work, we elaborate on the connection-based routing strategy and algorithmic enhancements to improve the serial FPGA routing. We also explore a recursive partitioning-based parallelization technique to further accelerate the routing process. To exploit more parallelism by a finer granularity in both spatial partitioning and routing, a connection-aware routing bounding box model is proposed for the source-sink connections of the nets. It is built upon the location information of each connection’s source, sink, and the geometric center of the net that the connection belongs to, different from the existing net-based routing bounding box that covers all the pins of the entire net. We present that the proposed connection-aware routing bounding box is more beneficial for parallel routing than the existing net-based routing bounding box. The quality and runtime of the serial and multi-threaded routers are compared to the router in VPR 7.0.7. The large heterogeneous Titan23 designs that are targeted to a detailed representation of the Stratix IV FPGA are used for benchmarking. With eight threads, the parallel router using the connection-aware routing bounding box model reaches a speedup of 6.1× over the serial router in VPR 7.0.7, which is 1.24× faster than the one using the existing net-based routing bounding box model, while reducing the total wire-length by 10% and the critical path delay by 7%.
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