Reliability, degradation and breakdown of advanced gate stacks

When a metal-oxide-semiconductor (MOS) structure is subjected to electrical stress, traps or defects are progressively generated within the insulator and at the interfaces, a process that eventually leads to the formation of a filamentary path across the gate dielectric. This is the signature of dielectric breakdown and is a major reliability issue for MOSFET devices. The problem is that not all the gate stacks break down in the same way so that a detailed analysis for each particular system is required. Although the failure statistics of thin oxide layers has been shown to be consistent with percolation models of defects generation, much less is known about the physics of post-breakdown conduction. In the last decade, several models based on mechanisms such as variable range hopping, tunneling, percolation and quantum point contact conduction have been proposed to explain the electron transport through the oxide layer under such circumstances. In this presentation, we will review the physics associated with these models starting from basic oxide reliability analysis. Some circuit implications of broken down devices and current applications such as the resistive switching effect will also be discussed.