K. Ishibashi, S. Ohbayashi, K. Eikyu, M. Tanizawa, Y. Tsukamoto, K. Osada, M. Miyazaki, M. Yamaoka
{"title":"降低SOC功耗的电路技术和晶体管模型问题","authors":"K. Ishibashi, S. Ohbayashi, K. Eikyu, M. Tanizawa, Y. Tsukamoto, K. Osada, M. Miyazaki, M. Yamaoka","doi":"10.1109/IEDM.2006.346996","DOIUrl":null,"url":null,"abstract":"The obstacles for low power SOC are leakage and variability of MOS transistors. Many circuit techniques have been proposed to tackle these issues. An adaptive body bias technique for logics and a source line voltage control technique for memories are inevitable techniques. Precise analysis of timing for logics and electrical stability for memories are keys to optimizing low voltage operations and they need precise Spice models that handle the variability","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Circuit Technologies for Reducing the Power of SOC and Issues on Transistor Models\",\"authors\":\"K. Ishibashi, S. Ohbayashi, K. Eikyu, M. Tanizawa, Y. Tsukamoto, K. Osada, M. Miyazaki, M. Yamaoka\",\"doi\":\"10.1109/IEDM.2006.346996\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The obstacles for low power SOC are leakage and variability of MOS transistors. Many circuit techniques have been proposed to tackle these issues. An adaptive body bias technique for logics and a source line voltage control technique for memories are inevitable techniques. Precise analysis of timing for logics and electrical stability for memories are keys to optimizing low voltage operations and they need precise Spice models that handle the variability\",\"PeriodicalId\":366359,\"journal\":{\"name\":\"2006 International Electron Devices Meeting\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2006.346996\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2006.346996","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Circuit Technologies for Reducing the Power of SOC and Issues on Transistor Models
The obstacles for low power SOC are leakage and variability of MOS transistors. Many circuit techniques have been proposed to tackle these issues. An adaptive body bias technique for logics and a source line voltage control technique for memories are inevitable techniques. Precise analysis of timing for logics and electrical stability for memories are keys to optimizing low voltage operations and they need precise Spice models that handle the variability
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