{"title":"加速STT-MRAM爬坡特性","authors":"Govind Radhakrishnan, Y. Yoon, M. Sachdev","doi":"10.1109/newcas49341.2020.9159842","DOIUrl":null,"url":null,"abstract":"Systematic characterization is crucial for magnetic tunnel junction from initial stack development to the final mass production. It has a direct impact on the wafer turn-around time and time to market. Under these circumstances, device characterization of the magnetic tunnel junction (MTJ) stack configuration is a critical step in the product development cycle. This paper reviews the challenges and advancements in spin torque transfer (STT)-magnetoresistive random access memory (MRAM) characterization and testing over the past decade that has accelerated the fabrication process ramp-up. We also provide an overview of a design-for-testability (DFT) scheme that can be used for parametric sensitivity analysis and a built-in-self-test (BIST) scheme that utilizes the DFT for bit-cell health monitoring in STT-MRAMs. The proposed schemes open new avenues for testing and characterization.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Accelerating STT-MRAM Ramp-up Characterization\",\"authors\":\"Govind Radhakrishnan, Y. Yoon, M. Sachdev\",\"doi\":\"10.1109/newcas49341.2020.9159842\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Systematic characterization is crucial for magnetic tunnel junction from initial stack development to the final mass production. It has a direct impact on the wafer turn-around time and time to market. Under these circumstances, device characterization of the magnetic tunnel junction (MTJ) stack configuration is a critical step in the product development cycle. This paper reviews the challenges and advancements in spin torque transfer (STT)-magnetoresistive random access memory (MRAM) characterization and testing over the past decade that has accelerated the fabrication process ramp-up. We also provide an overview of a design-for-testability (DFT) scheme that can be used for parametric sensitivity analysis and a built-in-self-test (BIST) scheme that utilizes the DFT for bit-cell health monitoring in STT-MRAMs. The proposed schemes open new avenues for testing and characterization.\",\"PeriodicalId\":135163,\"journal\":{\"name\":\"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/newcas49341.2020.9159842\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/newcas49341.2020.9159842","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Systematic characterization is crucial for magnetic tunnel junction from initial stack development to the final mass production. It has a direct impact on the wafer turn-around time and time to market. Under these circumstances, device characterization of the magnetic tunnel junction (MTJ) stack configuration is a critical step in the product development cycle. This paper reviews the challenges and advancements in spin torque transfer (STT)-magnetoresistive random access memory (MRAM) characterization and testing over the past decade that has accelerated the fabrication process ramp-up. We also provide an overview of a design-for-testability (DFT) scheme that can be used for parametric sensitivity analysis and a built-in-self-test (BIST) scheme that utilizes the DFT for bit-cell health monitoring in STT-MRAMs. The proposed schemes open new avenues for testing and characterization.