{"title":"混合微电子热建模","authors":"D. Reed, B. Gartner","doi":"10.1109/REG5.1988.15938","DOIUrl":null,"url":null,"abstract":"An outline is presented of a computer thermal analysis model that inputs information for existing computer-aided design (CAD) layout files. This model assumes conductive heat flow to determine the difference in temperature from the junction-to-case for multiple heat sources and uses this information to create a CAD-compatible drawing of the isotherms. The development and input/output of the model are discussed. The model is verified by using experimental data obtained from hybrids built-up with thermal test chips.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Thermal modeling of hybrid microelectronics\",\"authors\":\"D. Reed, B. Gartner\",\"doi\":\"10.1109/REG5.1988.15938\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An outline is presented of a computer thermal analysis model that inputs information for existing computer-aided design (CAD) layout files. This model assumes conductive heat flow to determine the difference in temperature from the junction-to-case for multiple heat sources and uses this information to create a CAD-compatible drawing of the isotherms. The development and input/output of the model are discussed. The model is verified by using experimental data obtained from hybrids built-up with thermal test chips.<<ETX>>\",\"PeriodicalId\":126733,\"journal\":{\"name\":\"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-03-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/REG5.1988.15938\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/REG5.1988.15938","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An outline is presented of a computer thermal analysis model that inputs information for existing computer-aided design (CAD) layout files. This model assumes conductive heat flow to determine the difference in temperature from the junction-to-case for multiple heat sources and uses this information to create a CAD-compatible drawing of the isotherms. The development and input/output of the model are discussed. The model is verified by using experimental data obtained from hybrids built-up with thermal test chips.<>
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