Measuring memory access latency for software objects in a NUMA system-on-chip architecture

We consider streaming applications modeled as a set of tasks communicating via channels. These channels are mapped to on-chip memory of a multi-processor system on chip (MPSoC) with non-uniform memory access. In complex applications like advanced packet processing and video streaming, often only part of the data transits through the channels. Tasks also communicate via shared memory; synchronization mechanisms like locks and barriers might be required. Effects of I/O on the traffic on the interconnect also have to be taken into account, all together increasing traffic to and from memory. Our clustered MPSoC architecture is modeled with SoCLib. SocLib's design space exploration tool proposes, among others, communication channels and shared memory for inter-task communication. Each consists of one of several software objects which are mapped to on-chip memory. The difficulty when measuring latency is to find out which (co-)processor issued a request for a particular software object. We intervene early in the design process by monitoring the transfers on the interconnection network caused by the access to these software objects. We identify the software objects by name and trace the corresponding memory accesses. In spite of the cycle accurate bit accurate level of simulation, our method has little overhead and avoids distorting the performance results.