{"title":"使用FormalCheck对Fairisle ATM交换机结构进行模型检查","authors":"L. Barakatain, S. Tahar","doi":"10.1109/CCECE.2001.933562","DOIUrl":null,"url":null,"abstract":"We describe the model checking of an asynchronous transfer mode (ATM) network switch fabric using the FormalCheck tool. The switch we considered is in use for real applications in the Cambridge Fairisle network. For the current verification in FormalCheck, we used the same Verilog HDL code as Lu and Tahar (see Proc. IEEE 8th Great Lakes Symposium on VLSI, Lafayette, Louisiana, USA, p.368-73, 1998) with some modifications. We specified and verified in FormalCheck a set of liveness and safety properties against several model sizes of the switch fabric. First, we verified an abstracted (1-bit) model of the switch fabric, which was already verified using VIS. Then, we accomplished the verification of a 4-bit model, and the full 8-bit model. We furthermore provide a comparative study between the verification results in VIS and FormalCheck.","PeriodicalId":184523,"journal":{"name":"Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Model checking of the Fairisle ATM switch fabric using FormalCheck\",\"authors\":\"L. Barakatain, S. Tahar\",\"doi\":\"10.1109/CCECE.2001.933562\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We describe the model checking of an asynchronous transfer mode (ATM) network switch fabric using the FormalCheck tool. The switch we considered is in use for real applications in the Cambridge Fairisle network. For the current verification in FormalCheck, we used the same Verilog HDL code as Lu and Tahar (see Proc. IEEE 8th Great Lakes Symposium on VLSI, Lafayette, Louisiana, USA, p.368-73, 1998) with some modifications. We specified and verified in FormalCheck a set of liveness and safety properties against several model sizes of the switch fabric. First, we verified an abstracted (1-bit) model of the switch fabric, which was already verified using VIS. Then, we accomplished the verification of a 4-bit model, and the full 8-bit model. We furthermore provide a comparative study between the verification results in VIS and FormalCheck.\",\"PeriodicalId\":184523,\"journal\":{\"name\":\"Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-05-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CCECE.2001.933562\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCECE.2001.933562","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
摘要
我们描述了使用FormalCheck工具对异步传输模式(ATM)网络交换结构进行模型检查。我们考虑的交换机在剑桥Fairisle网络的实际应用中使用。对于FormalCheck中的当前验证，我们使用了与Lu和Tahar相同的Verilog HDL代码(参见Proc. IEEE第八届VLSI大湖研讨会，Lafayette, Louisiana, USA, p.368- 73,1998)，并进行了一些修改。我们在FormalCheck中指定并验证了针对几种型号尺寸的交换机结构的一组活动性和安全性属性。首先，我们验证了一个抽象的(1位)交换结构模型，该模型已经使用VIS进行了验证。然后，我们完成了4位模型的验证，以及完整的8位模型的验证。并对VIS和FormalCheck的验证结果进行了对比研究。
Model checking of the Fairisle ATM switch fabric using FormalCheck
We describe the model checking of an asynchronous transfer mode (ATM) network switch fabric using the FormalCheck tool. The switch we considered is in use for real applications in the Cambridge Fairisle network. For the current verification in FormalCheck, we used the same Verilog HDL code as Lu and Tahar (see Proc. IEEE 8th Great Lakes Symposium on VLSI, Lafayette, Louisiana, USA, p.368-73, 1998) with some modifications. We specified and verified in FormalCheck a set of liveness and safety properties against several model sizes of the switch fabric. First, we verified an abstracted (1-bit) model of the switch fabric, which was already verified using VIS. Then, we accomplished the verification of a 4-bit model, and the full 8-bit model. We furthermore provide a comparative study between the verification results in VIS and FormalCheck.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
