{"title":"DSP平台的嵌入式调试和跟踪接口基础结构","authors":"Ming-Chang Hsieh, Chih-Tsun Huang","doi":"10.1145/1391469.1391688","DOIUrl":null,"url":null,"abstract":"The paper presents an infrastructure for debug and trace of the embedded digital signal processor (DSP) system, consisting of the in-system trace interface and its methodology to optimize the compression rate of the program and data traces. The platform has been implemented in a multimedia dual-core SOC design with little area overhead. Both the benchmark evaluation and realistic system integration justified the efficiency and effectiveness of our approach.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"An embedded infrastructure of debug and trace interface for the DSP platform\",\"authors\":\"Ming-Chang Hsieh, Chih-Tsun Huang\",\"doi\":\"10.1145/1391469.1391688\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents an infrastructure for debug and trace of the embedded digital signal processor (DSP) system, consisting of the in-system trace interface and its methodology to optimize the compression rate of the program and data traces. The platform has been implemented in a multimedia dual-core SOC design with little area overhead. Both the benchmark evaluation and realistic system integration justified the efficiency and effectiveness of our approach.\",\"PeriodicalId\":412696,\"journal\":{\"name\":\"2008 45th ACM/IEEE Design Automation Conference\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-06-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 45th ACM/IEEE Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1391469.1391688\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 45th ACM/IEEE Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1391469.1391688","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An embedded infrastructure of debug and trace interface for the DSP platform
The paper presents an infrastructure for debug and trace of the embedded digital signal processor (DSP) system, consisting of the in-system trace interface and its methodology to optimize the compression rate of the program and data traces. The platform has been implemented in a multimedia dual-core SOC design with little area overhead. Both the benchmark evaluation and realistic system integration justified the efficiency and effectiveness of our approach.
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