Mapping systolic algorithms into shuffle arrays

A generic data-flow architecture for mapping large computation problems is designed. The architecture is based on reconfigurable shuffle buses, by which the complexity of interprocessor communications is largely simplified. The issues of representing the computation problems, deriving routing schemes for a generic linear array, and resolving the pipelining of multiple data flows are addressed. It is shown that the shuffle bus provides a very efficient interconnection network for both data shuffling and I/O interface.<>