模板从VHDL合成

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186201

Z. Navabi, J. Spillane

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引用次数: 6

摘要

给出了两种可合成的VHDL描述样式模板及其相应的硬件。一种风格是在数据流级别使用显式时钟方案。另一种使用行为VHDL描述功能，并使用数据流进行架构规范。

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Templates for synthesis from VHDL

Two templates for synthesizable VHDL description styles and their corresponding hardware are presented. One style is at the dataflow level with an explicit clocking scheme. The other uses behavioral VHDL for describing functionality and dataflow for architectural specification.<>

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

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