1 ~ 5v工作1mb全CMOS SRAM的高速低备用功耗电路设计

Symposium 1993 on VLSI Circuits Pub Date : 1993-05-19 DOI:10.1109/VLSIC.1993.920564

T. Yabe, F. Matsuoka, K. Sato, S. Hayakawa, M. Matsui, A. Aono, H. Yoshimura, K. Ishimaru, H. Gojohbori, S. Morita, Y. Unno, M. Kakumu, K. Ochii

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引用次数: 5

摘要

本文介绍了1 ~ 5v工作1mb全CMOS SRAM的高速低备用功耗电路设计。目前已经报道了几种1v工作的sram，但没有一种能够同时在1v下实现200ns的快速访问时间和在1-3 V范围内低于0.1 /spl mu/W的低待机功率。这款1Mb SRAM设计用于实现上述性能，适用于1.5 V电池操作应用和3 V使用。多种电路技术如多vth CMOS门、开关延迟线脉冲发生器(SDLPG)和电阻插入式电流镜像检测放大器(RCSA)已被开发出来。

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High-speed and low-standby-power circuit design of 1 to 5 V operating 1 Mb full CMOS SRAM

This paper describes high-speed and low-standby-power circuit design of 1 to 5 V operating 1 Mb full CMOS SRAM. Several 1 V operating SRAMs have been reported so far, but none of them achieves both fast access time of 200 ns at 1 V and low standby power below O.1 /spl mu/W under 1-3 V range compatibly. This 1Mb SRAM is designed to achieve the performance above, which is suitable for both 1.5 V battery-operational application and 3 V use. Several circuit techniques such as Multi-Vth CMOS gates, Switched Delay-Line Pulse Generator ( SDLPG) and Resistor-inserted Current mirror sense Amplifier (RCSA) have been developed.

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Symposium 1993 on VLSI Circuits

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