LDD对SOI NMOS晶体管老化的影响

G. Reimbold, P. Saint Bonnet, B. Giffard, A. Auberton-Herve
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引用次数: 1

摘要

研究了两种低掺杂漏极(LDD)结构下1.3 μ m绝缘体上硅(SOI) CMOS晶体管的老化特性。观察到热载流子效应的基本差异,并澄清了对可靠性的影响。晶体管的整体性能对LDD优化非常敏感:低n掺杂可以获得较低的电离率、良好的阻塞电压和老化过程中固有的VG/sub /增加;高N-,尽管小的低时移,必须谨慎使用,如果初始阻塞特性和双极效应是至关重要的。在这种情况下,体积晶体管推荐(必须使用高N-以保持晶体管栅极下的高电场)可能不适合SOI晶体管
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Influence of LDD on aging of SOI NMOS transistors
Aging characteristics of 1.3- mu m silicon-on-insulator (SOI) CMOS transistors were studied for two different low doped drain (LDD) configurations. Fundamental differences concerning hot carrier effects were observed, and the impact on reliability was clarified. It appears that overall transistor performances are very sensitive to LDD optimization: low N-doping is recommended for low ionization rate, subsequent good blocking voltage, and intrinsic VG/sub bl/ increase during aging; high N-, in spite of small low time shifts, must be used carefully if initial blocking characteristics and bipolar effects are critical. In such cases, bulk transistor recommendations (high N- must be used in order to maintain high electric field under the transistor gate) may not be suitable for SOI transistors.<>
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