{"title":"FDCT算法的组合结构","authors":"A. Sanyal, S. Samaddar","doi":"10.1109/ICCCT.2012.16","DOIUrl":null,"url":null,"abstract":"A single generalized architecture has been deviced which can perform 4 FDCT algorithms namely, Arai's, Chen's, Loeffler's and Vetterli's by varying the control signals. Simulink files containing block design files of 4 FDCT algorithms are included. From the Simulink file appropriate language (VHDL) for the target board (FPGA) can be generated. The VHDL code is run in MODELSIM XE III/Starter 6.1e-custom Xilinx Version. Here the target board is XILINX VIRTEX-IV PRO. The obtained results are compared and concluded.","PeriodicalId":235770,"journal":{"name":"2012 Third International Conference on Computer and Communication Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A Combined Architecture for FDCT Algorithm\",\"authors\":\"A. Sanyal, S. Samaddar\",\"doi\":\"10.1109/ICCCT.2012.16\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single generalized architecture has been deviced which can perform 4 FDCT algorithms namely, Arai's, Chen's, Loeffler's and Vetterli's by varying the control signals. Simulink files containing block design files of 4 FDCT algorithms are included. From the Simulink file appropriate language (VHDL) for the target board (FPGA) can be generated. The VHDL code is run in MODELSIM XE III/Starter 6.1e-custom Xilinx Version. Here the target board is XILINX VIRTEX-IV PRO. The obtained results are compared and concluded.\",\"PeriodicalId\":235770,\"journal\":{\"name\":\"2012 Third International Conference on Computer and Communication Technology\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-11-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 Third International Conference on Computer and Communication Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCCT.2012.16\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Third International Conference on Computer and Communication Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCCT.2012.16","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A single generalized architecture has been deviced which can perform 4 FDCT algorithms namely, Arai's, Chen's, Loeffler's and Vetterli's by varying the control signals. Simulink files containing block design files of 4 FDCT algorithms are included. From the Simulink file appropriate language (VHDL) for the target board (FPGA) can be generated. The VHDL code is run in MODELSIM XE III/Starter 6.1e-custom Xilinx Version. Here the target board is XILINX VIRTEX-IV PRO. The obtained results are compared and concluded.