基于吠陀乘法技术的浮点乘法器的设计与实现

2012 International Conference on Communication, Information & Computing Technology (ICCICT) Pub Date : 2012-12-31 DOI:10.1109/ICCICT.2012.6398204

Aniruddha Kanhe, S. K. Das, Ankit Kumar Singh

{"title":"基于吠陀乘法技术的浮点乘法器的设计与实现","authors":"Aniruddha Kanhe, S. K. Das, Ankit Kumar Singh","doi":"10.1109/ICCICT.2012.6398204","DOIUrl":null,"url":null,"abstract":"In this paper, Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. The Urdhva-triyakbhyam sutra is used for the multiplication of Mantissa. The underflow and over flow cases are handled. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The multiplier is implemented in VHDL and Virtex-5 FPGA is used.","PeriodicalId":319467,"journal":{"name":"2012 International Conference on Communication, Information & Computing Technology (ICCICT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"45","resultStr":"{\"title\":\"Design and implementation of floating point multiplier based on Vedic Multiplication Technique\",\"authors\":\"Aniruddha Kanhe, S. K. Das, Ankit Kumar Singh\",\"doi\":\"10.1109/ICCICT.2012.6398204\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. The Urdhva-triyakbhyam sutra is used for the multiplication of Mantissa. The underflow and over flow cases are handled. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The multiplier is implemented in VHDL and Virtex-5 FPGA is used.\",\"PeriodicalId\":319467,\"journal\":{\"name\":\"2012 International Conference on Communication, Information & Computing Technology (ICCICT)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"45\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 International Conference on Communication, Information & Computing Technology (ICCICT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCICT.2012.6398204\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Conference on Communication, Information & Computing Technology (ICCICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCICT.2012.6398204","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 45

摘要

本文采用吠陀乘法技术实现ieee754浮点乘法器。Urdhva-triyakbhyam经是用来增加尾数的。处理了下流和上流情况。乘法器的输入采用IEEE 754,32位格式。该乘法器采用VHDL语言和Virtex-5 FPGA实现。

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Design and implementation of floating point multiplier based on Vedic Multiplication Technique

In this paper, Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. The Urdhva-triyakbhyam sutra is used for the multiplication of Mantissa. The underflow and over flow cases are handled. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The multiplier is implemented in VHDL and Virtex-5 FPGA is used.

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2012 International Conference on Communication, Information & Computing Technology (ICCICT)

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