{"title":"用于高速网络的VLSI间隔路由器","authors":"B. Christian, C.N. Zhang, R. Mason","doi":"10.1109/CCECE.1996.548060","DOIUrl":null,"url":null,"abstract":"In this work, a VLSI wormhole router for scalable high-speed networks including 2-D mesh, nearest-neighbor, and n-cube interconnected networks has been developed and implemented. The router is deadlock-free and guarantees to form the shortest paths. This VLSI router has been implemented and fabricated by using 1.2 /spl mu/ CMOS4S standard cell library consisting of 65,000 gates. The performance of the VLSI router is measured and modeled.","PeriodicalId":269440,"journal":{"name":"Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A VLSI interval router for high-speed networks\",\"authors\":\"B. Christian, C.N. Zhang, R. Mason\",\"doi\":\"10.1109/CCECE.1996.548060\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, a VLSI wormhole router for scalable high-speed networks including 2-D mesh, nearest-neighbor, and n-cube interconnected networks has been developed and implemented. The router is deadlock-free and guarantees to form the shortest paths. This VLSI router has been implemented and fabricated by using 1.2 /spl mu/ CMOS4S standard cell library consisting of 65,000 gates. The performance of the VLSI router is measured and modeled.\",\"PeriodicalId\":269440,\"journal\":{\"name\":\"Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-05-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CCECE.1996.548060\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCECE.1996.548060","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this work, a VLSI wormhole router for scalable high-speed networks including 2-D mesh, nearest-neighbor, and n-cube interconnected networks has been developed and implemented. The router is deadlock-free and guarantees to form the shortest paths. This VLSI router has been implemented and fabricated by using 1.2 /spl mu/ CMOS4S standard cell library consisting of 65,000 gates. The performance of the VLSI router is measured and modeled.
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