ENFIRE:一种节能的细粒度时空可重构计算结构

Wenchao Qian, Christopher Babecki, Robert Karam, S. Bhunia
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引用次数: 0

摘要

现场可编程门阵列(fpga)是公认的细粒度硬件可重构计算平台。然而,FPGA的能量使用主要是可编程互连,它在不同技术世代之间具有较差的可扩展性。在这项工作中,我们提出了ENFIRE,一种新颖的、节能的、细粒度的、时空的、基于内存的可重构计算框架,它提供了比特级信息处理的灵活性,这在传统的粗粒度可重构架构(CGRAs)中是不可用的。密集的二维存储阵列是所提出的框架中的主要计算元素,它不仅存储要处理的数据,而且还以各种输入/输出大小的查找表(lut)的形式存储映射应用程序的功能行为。空间分布的可配置计算元素(CE)使用网格网络基于数据依赖相互通信,而每个CE内部的执行以临时方式进行。还共同开发了一个定制软件框架,使应用程序能够映射到一组ce。通过在空间和时间计算之间找到适当的平衡,它可以实现高能效的映射,与FPGA相比,显着降低了可编程互连的开销。仿真结果显示,与一组随机逻辑基准的可比较FPGA实现相比,总能量提高了7.6倍,能效提高了1.6倍,泄漏能量提高了1.1倍,统一能效提高了5.3倍,统一能效是一个同时考虑能量和面积的指标。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric (Abstact Only)
Field Programmable Gate Arrays (FPGAs) are well-established as fine-grained hardware reconfigurable computing platforms. However, FPGA energy usage is dominated by programmable interconnects, which have poor scalability across different technology generations. In this work, we propose ENFIRE, a novel, energy-efficient, fine-grained, spatio-temporal, memory-based reconfigurable computing framework that provides the flexibility of bit-level information processing, which is not available in conventional coarse-grain reconfigurable architectures (CGRAs). A dense two-dimensional memory array is the main computing element in the proposed framework, which stores not only the data to be processed, but also the functional behavior of a mapped application in the form of lookup tables (LUTs) of various input/output sizes. Spatially distributed configurable computing elements (CEs) communicate with each other based on data dependencies using a mesh network, while execution inside each CE occurs in a temporal manner. A custom software framework has also been co-developed which enables application mapping to a set of CEs. By finding the right balance between spatial and temporal computing, it can achieve a highly energy-efficient mapping, significantly reducing the programmable interconnect overhead when compared with FPGA. Simulation results show an improvement of 7.6X in overall energy, 1.6X in energy efficiency, 1.1X in leakage energy, and 5.3X in Unified Energy-Efficiency, a metric that considers energy and area together, compared with comparable FPGA implementations for a set of random logic benchmarks.
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