Designing low complexity computational intelligence modules in FPGA using high level synthesis tools

High level synthesis tools offered by either FPGA (Field Programmable Gate Array) vendors or from the public domain are evaluated in order to generate efficient and low complexity computational intelligence modules. This paper reports specific issues and comparative synthesis results in implementing basic modules of the FSVC classifier (Fast Support Vector Classifier) and cellular automata starting from an algorithmic description in high level languages such as Python and C/C++. Two particular HLS tools were considered, namely VivadoHLS from Xilinx and MyHDL.