计算机体系结构教育中基于FPGA的RISC-V处理器设计框架与工具

Tyler McGrew, Eric Schonauer
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引用次数: 9

摘要

可以说,每个计算机工程专业的本科生都应该在攻读学位的过程中构建一个简单的处理器,以帮助他们内化计算机的基本设计原则和特性。随着fpga在大学中的普及,这很容易在大多数本科课程中实现。许多关于计算机体系结构或组织的现代课程都依赖于MIPS体系结构(以及其他)作为学习的基础处理器,但是MIPS体系结构几乎没有商业上的成功和现实世界的实现,这将允许学生从构建和学习使用的体系结构中获得额外的职业利益。RISCV ISA日益增长的工业兴趣,它的免费可用性,以及它在现实世界中采用的早期成功,使这个处理器成为这个教育领域的一个极具潜力的候选人。这项工作为本科生如何在FPGA上构建RISC-V架构提供了建议,并为本练习提供了基本的工具框架和设计原则。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Framework and Tools for Undergraduates Designing RISC-V Processors on an FPGA in Computer Architecture Education
Arguably, each computer engineer undergrad should build a simple processor in the pursuit of their degree to help them internalize the basic design principles and properties of a computer. With the proliferation of FPGAs in universities this is, easily, realizable in most undergraduate curricula. Many modern courses on computer architecture or organization rely on MIPS architectures (among others) as the base processor to learn with, but the MIPS architecture has little commercial success and real-world implementations that will allow students to get additional career benefit from building and learning about a used architecture. The increasing industrial interest of RISCV ISA, its free availability, and its early success in real-world adoption makes this processor a great potential candidate in this educational space. This work provides suggestions on how undergraduates should build a RISC-V architecture on an FPGA, and a basic framework of tools and design principles for this exercise.
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