Implementation of PMOS Biased Sense Amplifier Using Tanner EDA tool

Sense amplifiers contribute to the effectiveness, practicality, and durability of memory devices. In the following paper, two new sense amplifier schematics seemed to enhance the performance of memory circuits. The suggested circuits, as opposed to traditional circuits, utilize a PMOS biasing strategy that allows for high output impedance while minimizing sensing delay and power consumption. The circuits function similarly to conventional sense amplifiers, however these circuits have been found to exhibit higher efficiency of their absorbed power and sensing delay. Presented sense amplifiers’ performance was evaluated through simulations leveraging Tanner EDA software and a 180nm technology. In accordance with simulations, the presented circuits functioned consistently with the theoretical analysis, demonstrating their sound design. The results of this study suggest that the sense amplifiers that have been suggested might improve the performance and usefulness of memory circuits found in a number of electronic devices. The reduced power consumption and sensor latency may lead to longer battery life and faster processing times, which may enhance user experience.