Optimal processor interface for CGRA-based accelerators implemented on FPGAs

Coarse Grained Reconfigurable Arrays (CGRA) can be used to substantially boost the processing power of embedded applications. They can be included in typical system-on-chip architectures to execute computationally demanding parts of the application. Delegating execution to the CGRA requires the exchange of live in/out variables between the processor core and the CGRA. In this paper we search the optimal interface between the surrounding system and the CGRA with respect to impact on the operating frequency, the used resources and the runtime overhead.