用于传感器网络应用的通用识别处理器

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2010-01-18 DOI:10.1109/ASPDAC.2010.5419867

R. Takashima, Yuya Hanai, Y. Hori, T. Kuroda

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引用次数: 0

摘要

提出了一种采用90纳米CMOS技术，由2.1M晶体管组成的多功能识别处理器。它对图像/视频、声音和加速度信号进行检测和识别，能耗低于mj /帧。采用类哈尔特征和级联分类器的优化结构设计，提高了系统的通用性和功耗效率。

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A versatile recognition processor for sensor network applications

A versatile recognition processor is presented that comprises 2.1M transistors using a 90nm CMOS technology. It performs detection and recognition from image/video, sound and acceleration signals with energy consumption of sub-mJ/frame. The versatility and the power efficiency are attributed to optimal architecture design employing Haar-like Feature and Cascaded Classifier.

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来源期刊

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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