Efficient FPGA Floorplanning for Partial Reconfiguration-Based Applications

This paper introduces an efficient automatic floorplanning algorithm, which takes into account the heterogeneous architectures of modern FPGA families, as well as partial reconfiguration (PR) constraints, introducing the aspect ratio (AR) constraint to optimize routing. The algorithm generates possible placements of the partial modules, and then applies a recursive pseudo-bipartitioning heuristic search to find the best floorplan. The experiments show that its performance is significantly better than the one of other algorithms in this field.