基于自定时异步电路元件的FIFO设计与仿真

Proceedings of the Fifteenth National Radio Science Conference. NRSC '98 (Cat. No.98EX109) Pub Date : 1998-02-24 DOI:10.1109/NRSC.1998.711467

H. T. Bahbouh, A. Ezzat Salama, A. Khalil

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摘要

本文的目的是介绍异步电路设计中用到的基本元件。实现了CMOS设计。利用SPICE模拟器对这些元件的性能进行了评估。FIFO流水线结构利用自定时异步元件实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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The design and simulation of FIFO using self-timed based asynchronous circuit elements

The objective of this paper is to introduce the basic elements utilized in the design of asynchronous circuits. CMOS designs are implemented. The performance of these elements is evaluated using SPICE simulator. FIFO pipelined structure was implemented utilizing self-timed asynchronous elements.

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Proceedings of the Fifteenth National Radio Science Conference. NRSC '98 (Cat. No.98EX109)

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