Firsynth:用于高级FIR滤波器合成的CAD工具

2014 Fifth Argentine Symposium and Conference on Embedded Systems SASE/CASE 2014 Pub Date : 2014-10-02 DOI:10.1109/SASE-CASE.2014.6914460

O. Alpago, Federico G. Zacchigna, A. Lutenberg

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引用次数: 0

摘要

介绍了一种用于高级合成有限脉冲响应(FIR)滤波器的软件工具。该工具基于正则符号数字(CSD)编码的滤波系数和非递归符号公共子表达式消除算法(NR-SCSE)的逻辑算子(加法器和减法器)最小化。通过该工具，可以生成适合于现场可编程门阵列(FPGA)和专用集成电路(ASIC)的完全可合成的HDL代码。本文描述了所有实现的算法。逻辑算子(LOs)是基于纹波进位结构(RCS)，以节省面积和简化路由。源代码是用C语言开发的，可以在GNU通用公共许可证(GNU- gpl)下使用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Firsynth: A CAD tool for high-level FIR filter synthesis

A software tool for high-level synthesis of Finite Impulse Response (FIR) filters is presented. The tool is based on Canonic Signed Digit (CSD) coding for filter coefficients and Nonrecursive Signed Common Subexpression Elimination algorithm (NR-SCSE) for logic operators (adders and subtractors) mini-mization. By means of this tool a fully-synthesizable HDL code can be generated which is suitable for Field Programmable Gates Arrays (FPGA) as well as for Application Specific Integrated Circuits (ASIC). In this paper all the algorithms implemented are described. Logic operators (LOs) are based on ripple carry structures (RCS) in order to save area and simplify routing. The source code was developed in C programming language and can be used under GNU General Public License (GNU-GPL).

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2014 Fifth Argentine Symposium and Conference on Embedded Systems SASE/CASE 2014

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