{"title":"一种采用数字0.35 /spl μ l /m CMOS工艺的5 GHz低功耗、高线性低噪声放大器","authors":"J. Fairbanks, L. Larson","doi":"10.1109/RAWCON.2003.1227968","DOIUrl":null,"url":null,"abstract":"A 5 GHz low noise amplifier (LNA), intended for use in a wireless local area network (WLAN) receiver, has been implemented in a standard digital 0.35 /spl mu/m CMOS process. The amplifier provides a power gain of 9.0 dB while consuming 11 mW from a 2.2 V supply and reaches 6.0 dBm at third order input intermodulation intercept point (IIIP3). In this paper, we present a brief analysis of the LNA architecture and experimental results.","PeriodicalId":177645,"journal":{"name":"Radio and Wireless Conference, 2003. RAWCON '03. Proceedings","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 5 GHz low-power, high-linearity low-noise amplifier in a digital 0.35 /spl mu/m CMOS process\",\"authors\":\"J. Fairbanks, L. Larson\",\"doi\":\"10.1109/RAWCON.2003.1227968\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 5 GHz low noise amplifier (LNA), intended for use in a wireless local area network (WLAN) receiver, has been implemented in a standard digital 0.35 /spl mu/m CMOS process. The amplifier provides a power gain of 9.0 dB while consuming 11 mW from a 2.2 V supply and reaches 6.0 dBm at third order input intermodulation intercept point (IIIP3). In this paper, we present a brief analysis of the LNA architecture and experimental results.\",\"PeriodicalId\":177645,\"journal\":{\"name\":\"Radio and Wireless Conference, 2003. RAWCON '03. Proceedings\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-09-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Radio and Wireless Conference, 2003. RAWCON '03. Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RAWCON.2003.1227968\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Radio and Wireless Conference, 2003. RAWCON '03. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RAWCON.2003.1227968","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 5 GHz low-power, high-linearity low-noise amplifier in a digital 0.35 /spl mu/m CMOS process
A 5 GHz low noise amplifier (LNA), intended for use in a wireless local area network (WLAN) receiver, has been implemented in a standard digital 0.35 /spl mu/m CMOS process. The amplifier provides a power gain of 9.0 dB while consuming 11 mW from a 2.2 V supply and reaches 6.0 dBm at third order input intermodulation intercept point (IIIP3). In this paper, we present a brief analysis of the LNA architecture and experimental results.
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