Novel harmonic elimination technique for cascaded H-bridge inverter using sampled reference frame

This paper proposes SWARM Intelligence based algorithm for selective harmonic elimination using SSVPWM in modified H-bridge multilevel inverter. This algorithm uses sampled reference frame to generate reference sine signal. The computation time is less as compared to that of sector identification algorithms. Also SWARM intelligence based algorithm doesn't require any look-up table potentiometer connected to ADC channel of this PIC which decides the V/F ratio and the keypad connected to PORTC which decides the harmonic order that has to be eliminated. The hardware setup for the proposed method for 5-level inverter has been developed successfully for 2.2 Kw Induction motor. The experimental result shows that this method can effectively reduce the selective harmonic in modified cascaded H-Bridge Multilevel inverter.