High speed VLSI implementation of lifting based DWT

Efficient line based hardware architecture for the lifting based discrete wavelet of an image is proposed in this work. Lifting Scheme reduces the number of operations execution steps to almost one-half of those needed with a conventional convolution approach. Performance comparison of simulation results for lifting DWT using MATLAB and VHDL is done to verify the proper functionality of the developed module. The comparison of direct mapped and folded VLSI architectures for lifting schemes is presented in terms of speed and hardware requirements. The whole architecture is being optimized to achieve better speed up and higher hardware utilization by using a single clock for predict and update operation. The proposed architecture is implemented in Xilinx Spartan 3E FPGA. The data flow of the proposed architecture is regular, simple, control complexity and achieves 100% hardware utilization. The entire system runs at faster rate and reaches a speed performance suitable for real time stand-alone image/video applications.