一种用于数百像素CMOS图像传感器的13位高速两步单斜率ADC设计方法

2022 IEEE 5th International Conference on Electronics Technology (ICET) Pub Date : 2022-05-13 DOI:10.1109/icet55676.2022.9825414

Ruiming Xu, Zhongjie Guo, Xinqi Cheng, Changxu Su, Chen Li, Yangle Wang

{"title":"一种用于数百像素CMOS图像传感器的13位高速两步单斜率ADC设计方法","authors":"Ruiming Xu, Zhongjie Guo, Xinqi Cheng, Changxu Su, Chen Li, Yangle Wang","doi":"10.1109/icet55676.2022.9825414","DOIUrl":null,"url":null,"abstract":"This paper proposes a 13-bit fully parallel two-step single slope (TS-SS)ADC for high speed CMOS image sensors. The ADC design method is based on the idea of time sharing and time compression, advances the fine conversion time to the coarse conversion time period, and solves the time redundancy problem of the traditional method. Based on the 55nm1P4M CMOS process, the differential nonlinearity (DNL) and the integral nonlinearity (INL) are simulated to be =0.8/−0.8 LSB and +2.1/−3.5LSB, respectively. The Conversion time of the 13-bit ADC is 512 ns. The effective number of bits (ENOB) is 11.33 bits and the power consumption is $47 \\mu$ W.","PeriodicalId":166358,"journal":{"name":"2022 IEEE 5th International Conference on Electronics Technology (ICET)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 13-Bit High Speed Two-Step Single Slope ADC Design Method for Hundreds of Mpxiel CMOS Image Sensors\",\"authors\":\"Ruiming Xu, Zhongjie Guo, Xinqi Cheng, Changxu Su, Chen Li, Yangle Wang\",\"doi\":\"10.1109/icet55676.2022.9825414\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a 13-bit fully parallel two-step single slope (TS-SS)ADC for high speed CMOS image sensors. The ADC design method is based on the idea of time sharing and time compression, advances the fine conversion time to the coarse conversion time period, and solves the time redundancy problem of the traditional method. Based on the 55nm1P4M CMOS process, the differential nonlinearity (DNL) and the integral nonlinearity (INL) are simulated to be =0.8/−0.8 LSB and +2.1/−3.5LSB, respectively. The Conversion time of the 13-bit ADC is 512 ns. The effective number of bits (ENOB) is 11.33 bits and the power consumption is $47 \\\\mu$ W.\",\"PeriodicalId\":166358,\"journal\":{\"name\":\"2022 IEEE 5th International Conference on Electronics Technology (ICET)\",\"volume\":\"67 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-05-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE 5th International Conference on Electronics Technology (ICET)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/icet55676.2022.9825414\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 5th International Conference on Electronics Technology (ICET)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icet55676.2022.9825414","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文提出了一种用于高速CMOS图像传感器的13位全并行两步单斜率(TS-SS)ADC。该ADC设计方法基于时间共享和时间压缩的思想，将精细转换时间推进到粗转换时间，解决了传统方法的时间冗余问题。基于55nm1P4M CMOS工艺，模拟了差分非线性(DNL)和积分非线性(INL)分别为=0.8/−0.8 LSB和+2.1/−3.5LSB。13位ADC的转换时间为512 ns。有效比特数(ENOB)为11.33比特，功耗为47美元。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 13-Bit High Speed Two-Step Single Slope ADC Design Method for Hundreds of Mpxiel CMOS Image Sensors

This paper proposes a 13-bit fully parallel two-step single slope (TS-SS)ADC for high speed CMOS image sensors. The ADC design method is based on the idea of time sharing and time compression, advances the fine conversion time to the coarse conversion time period, and solves the time redundancy problem of the traditional method. Based on the 55nm1P4M CMOS process, the differential nonlinearity (DNL) and the integral nonlinearity (INL) are simulated to be =0.8/−0.8 LSB and +2.1/−3.5LSB, respectively. The Conversion time of the 13-bit ADC is 512 ns. The effective number of bits (ENOB) is 11.33 bits and the power consumption is $47 \mu$ W.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2022 IEEE 5th International Conference on Electronics Technology (ICET)

自引率

0.00%

发文量