{"title":"无限实时系统的自动验证","authors":"Thomas Göthel, S. Glesner","doi":"10.1109/FormaliSE.2013.6612278","DOIUrl":null,"url":null,"abstract":"In safety-critical areas, complete and machine-assisted verification techniques for infinite real-time systems are required to ensure their correctness in all cases and to cope with their complexity. Previously, we presented a theorem prover-based comprehensive and compositional verification approach using the Timed CSP process calculus to model and verify possibly infinite real-time systems. However, it lacks support for employing automatic verification approaches to validate finite sub-processes of the overall system model. This mainly comes from insufficient automatic verification support for finite Timed CSP processes. In this paper, we present a real-time logic and a transformation of the Timed CSP process calculus to UPPAAL timed automata. We discuss their integration into our comprehensive verification approach as part of a prior validation phase. This is crucial because the effort for interactive verification in the theorem prover is thereby reduced considerably. By this, we provide a comprehensive machine-assisted verification approach without losing the benefits of automatic verification.","PeriodicalId":269932,"journal":{"name":"2013 1st FME Workshop on Formal Methods in Software Engineering (FormaliSE)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Automatic validation of infinite real-time systems\",\"authors\":\"Thomas Göthel, S. Glesner\",\"doi\":\"10.1109/FormaliSE.2013.6612278\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In safety-critical areas, complete and machine-assisted verification techniques for infinite real-time systems are required to ensure their correctness in all cases and to cope with their complexity. Previously, we presented a theorem prover-based comprehensive and compositional verification approach using the Timed CSP process calculus to model and verify possibly infinite real-time systems. However, it lacks support for employing automatic verification approaches to validate finite sub-processes of the overall system model. This mainly comes from insufficient automatic verification support for finite Timed CSP processes. In this paper, we present a real-time logic and a transformation of the Timed CSP process calculus to UPPAAL timed automata. We discuss their integration into our comprehensive verification approach as part of a prior validation phase. This is crucial because the effort for interactive verification in the theorem prover is thereby reduced considerably. By this, we provide a comprehensive machine-assisted verification approach without losing the benefits of automatic verification.\",\"PeriodicalId\":269932,\"journal\":{\"name\":\"2013 1st FME Workshop on Formal Methods in Software Engineering (FormaliSE)\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-05-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 1st FME Workshop on Formal Methods in Software Engineering (FormaliSE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FormaliSE.2013.6612278\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 1st FME Workshop on Formal Methods in Software Engineering (FormaliSE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FormaliSE.2013.6612278","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Automatic validation of infinite real-time systems
In safety-critical areas, complete and machine-assisted verification techniques for infinite real-time systems are required to ensure their correctness in all cases and to cope with their complexity. Previously, we presented a theorem prover-based comprehensive and compositional verification approach using the Timed CSP process calculus to model and verify possibly infinite real-time systems. However, it lacks support for employing automatic verification approaches to validate finite sub-processes of the overall system model. This mainly comes from insufficient automatic verification support for finite Timed CSP processes. In this paper, we present a real-time logic and a transformation of the Timed CSP process calculus to UPPAAL timed automata. We discuss their integration into our comprehensive verification approach as part of a prior validation phase. This is crucial because the effort for interactive verification in the theorem prover is thereby reduced considerably. By this, we provide a comprehensive machine-assisted verification approach without losing the benefits of automatic verification.