{"title":"抗单事件干扰(SEU)的12T抗辐射存储单元设计","authors":"Chunyan Hu, S. Yue, Shijin Lu","doi":"10.1109/ICAM.2017.8242164","DOIUrl":null,"url":null,"abstract":"A novel radiation hardened 12T memory cell (RH-12T) is proposed to address single event upset (SEU) problems in 65nm CMOS technology. It eliminates the possibility of a sensitive “0” storage node upset by surrounding the output nodes with NMOS, realizing a full resistance for any single node upset. Furthermore, less sensitive node pairs are obtained in circuit design compared to the DICE cell, which reduces the sensitivity to single event multiple-node upsets (SE-MNU). Hspice simulation shows that it has an excellent performance considering read and write access time with an acceptable SNM. Circuit-SEU simulation demonstrates that it is not only immune to upsets any single sensitive node, but also tolerant to multiple node upset on specific nodes with sharing charge of 100fC.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Design of a novel 12T radiation hardened memory cell tolerant to single event upsets (SEU)\",\"authors\":\"Chunyan Hu, S. Yue, Shijin Lu\",\"doi\":\"10.1109/ICAM.2017.8242164\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel radiation hardened 12T memory cell (RH-12T) is proposed to address single event upset (SEU) problems in 65nm CMOS technology. It eliminates the possibility of a sensitive “0” storage node upset by surrounding the output nodes with NMOS, realizing a full resistance for any single node upset. Furthermore, less sensitive node pairs are obtained in circuit design compared to the DICE cell, which reduces the sensitivity to single event multiple-node upsets (SE-MNU). Hspice simulation shows that it has an excellent performance considering read and write access time with an acceptable SNM. Circuit-SEU simulation demonstrates that it is not only immune to upsets any single sensitive node, but also tolerant to multiple node upset on specific nodes with sharing charge of 100fC.\",\"PeriodicalId\":117801,\"journal\":{\"name\":\"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)\",\"volume\":\"148 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICAM.2017.8242164\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAM.2017.8242164","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a novel 12T radiation hardened memory cell tolerant to single event upsets (SEU)
A novel radiation hardened 12T memory cell (RH-12T) is proposed to address single event upset (SEU) problems in 65nm CMOS technology. It eliminates the possibility of a sensitive “0” storage node upset by surrounding the output nodes with NMOS, realizing a full resistance for any single node upset. Furthermore, less sensitive node pairs are obtained in circuit design compared to the DICE cell, which reduces the sensitivity to single event multiple-node upsets (SE-MNU). Hspice simulation shows that it has an excellent performance considering read and write access time with an acceptable SNM. Circuit-SEU simulation demonstrates that it is not only immune to upsets any single sensitive node, but also tolerant to multiple node upset on specific nodes with sharing charge of 100fC.