Comparative performance analysis of multiplexer based single precision floating point multipliers

Floating-point arithmetic plays major role in computer systems. The single precision floating point arithmetic operations are multiplication, division, addition and subtraction. Among all these multiplication is extensively used and involves composite arithmetic functions. The single precision (32-bit) floating point number split into three parts namely Sign part, and Exponent part and Mantissa part. The most significant bit of the number is a sign bit and it is a 1-bit length. Next 8-bits represent the exponent part of the number and next 23-bits represent the mantissa part of the number. Mantissa part needs large 24-bit multiplication. The performance of the single-precision floating point number mostly based on the occupied area and delay of the multiplier. In this paper, performance comparison of multiplexer based single precision floating point multiplication using Array, Wallace tree and Vedic multipliers is done in terms of area and delay. These floating point multipliers modules are programmed and synthesized using Verilog in Xilinx ISE Simulator. Maximum propagated path delay and number of slices required on FPGA are compared for different multipliers. From the result it is concluded that Multiplexer based Vedic multiplier method has a great impact on improving the speed and reducing the area required on FPGA.