Endurance Enhancement of Multi-Level Cell Phase Change Memory

Phase change memory (PCM) is a promising device for its good scalability and negligible standby power consumption. Multi-level cell (MLC) PCM allows higher memory density, but it suffers from reduced endurance due to frequent RESET operations during writing. Inter-state direct write (ISDW) method is proposed, in which intermediate states ‘01’ and ‘10’ are reached without RESET initialization. A new MLC PCM model is presented, which takes account of phase configuration of each MLC PCM state; the feasibility of ISDW is assessed using the model. Compression-based RESET removal encoding (CRE) is also proposed to further reduce the number of RESET operations. Experiments demonstrate that the proposed methods achieve 38.4× enhancement of cell endurance; the writing energy dissipation is reduced to 31% on average of test cases.