{"title":"基于模糊逻辑的QRS复杂检测器的可测试ASIC设计","authors":"K. Azad, Z. M. Darus, M.A.M. Ali","doi":"10.1109/SMELEC.1998.781174","DOIUrl":null,"url":null,"abstract":"This paper presents an approach towards implementing a QRS detection algorithm into a single chip environment for maternal and fetal heart rate monitoring by using a fuzzy decision method to identify maternal and fetal QRS complexes from single-lead maternal abdominal recordings. A top-down design methodology was adopted during the design of the ASIC. Testability strategies were adopted in order to increase the ASIC reliability.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Testable ASIC design for a fuzzy logic based QRS complex detector\",\"authors\":\"K. Azad, Z. M. Darus, M.A.M. Ali\",\"doi\":\"10.1109/SMELEC.1998.781174\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an approach towards implementing a QRS detection algorithm into a single chip environment for maternal and fetal heart rate monitoring by using a fuzzy decision method to identify maternal and fetal QRS complexes from single-lead maternal abdominal recordings. A top-down design methodology was adopted during the design of the ASIC. Testability strategies were adopted in order to increase the ASIC reliability.\",\"PeriodicalId\":356206,\"journal\":{\"name\":\"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-11-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMELEC.1998.781174\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMELEC.1998.781174","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Testable ASIC design for a fuzzy logic based QRS complex detector
This paper presents an approach towards implementing a QRS detection algorithm into a single chip environment for maternal and fetal heart rate monitoring by using a fuzzy decision method to identify maternal and fetal QRS complexes from single-lead maternal abdominal recordings. A top-down design methodology was adopted during the design of the ASIC. Testability strategies were adopted in order to increase the ASIC reliability.