FPGA Implementation Of Reconfigurable Address Generator For Various Standard Interleaver

This paper describes a reconfigurable design for a multi-standard address generator and interleaver using a simpler technique. The importance of this effort is focused on the reuse of hardware. It also focuses on minimising hardware requirements in order to support numerous standards. The suggested multimode interleaver reduces hardware complexity by 60.28%. It supports 3GPP, LTE, WiMAX (802.16e), and WLAN (802.11a/b/g/n), protocols that operate at various modulation schemes and coding rates. The design is being operated with45 nm CMOS conventional cell technology and in synthesis of ASIC As a result, the data rate reconstructable address generator created. In comparison to the current condition of the address generators, latency will be reduced by 52.23%.