Overview and Comparison of Methodologies for Design in Deep Submicron CMOS Processes

The paper makes an overview and comparison of three popular methodologies used for design and sizing of analog CMOS circuits in deep submicron technologies. The following methodologies are considered: design with models, based on the threshold voltage; design with simplified EKV models; design with the gmJID methodology. The goal of the paper is to evaluate the use of these methodologies and their accuracy when used for hand calculations in the early stage of the design. For this purpose, the application of these three methodologies is demonstrated in the design of current mirror OTA in 45nm CMOS technology. The results from the sizing and the simulation of the circuit are analyzed and summarized.